Part Number Hot Search : 
GJ20N03 10E15 20120 SF3G48 AN5043SC 6642CU LI31040 HCT244
Product Description
Full Text Search
 

To Download RTL8201F-VB-CG Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
  RTL8201F-VB-CG rtl8201fl-vb-cg rtl8201fn-vb-cg single-chip/port 10/100m ethernet phyceiver with auto mdix datasheet (confidential: development partners only) rev. 1.4 30 november 2011 track id: jatr-2265-11 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix ii track id: jatr-2265-11 rev. 1.4 copyright ?2011 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document as is, without warranty of any kind. realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. this document could include technical inaccura cies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. license this product is covered by one or more of the following patents: us5,307,459, us5,434,872, us5,732,094, us6,570,884, us 6,115,776, and us6,327,625. using this document this document is intended for the software engin eers reference and provides detailed programming information. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix iii track id: jatr-2265-11 rev. 1.4 revision history revision release date summary 1.0 2010/12/17 first release. 1.1 2011/02/18 revised to vb model. revised table 22 register 30 interrupt indicators and snr display register, page 21. added interrupt function. added mmd register mapping and definition section. revised section 8.2 interrupt, page 31. revised table 46 absolute maximum ratings, page 44. revised 9.1.3 power on and phy reset sequence, page 45. revised table 49 rmii input mode power dissipation (whole system), page 46. 1.2 2011/04/21 revised figure 2 block diagram, page 4. revised table 3 rmii interface, page 10. revised table 7 device configuration interface, page 11. revised table 9 reset and other pins, page 14. revised table 11 register 0 basic mode control register, page 15. revised table 15 register 4 auto-negotiation advertisement register (anar), page 17. revised table 20 register 24, page 20. revised table 24 page4 register 16 eee capability enable register, page 22. revised table 25 page4 register 21 eee capability register, page 22. revised table 30 page7 register 19 , page 24. added section 7.21 page 7 register 24 spread spectrum clock register, page 25. revised section 8.1.2 serial management interface, page 29. revised section 8.7 reset and transmit bias, page 38. added section 8.13 spread spectrum clock (ssc), page 43. added figure 21 mii interface setup/hold time definitions, page 47. added figure 26 rmii interf ace setup, hold time, and output delay time definitions, page 49. added figure 28 mdc/mdio interface setup, ho ld time, and valid from mdc rising edge time definitions, page 51. 1.3 2011/07/14 added figure 1 application diagram, page 3. revised table 30 page7 register 19 interrupt, wol enable, and leds function registers, page 24. added table 34 eeepc1r (pcs control 1 register, mmd device 3, address 0x00), page 25. added table 35 eeeps1r (pcs status 1 register, mmd device 3, address 0x01), page 26. added section 8.4.1 led and phy address, page 32. added section 8.4.8 eee led, page 36. revised section 8.7 reset and transmit bias, page 38. 1.4 2011/11/30 revised figure 2 block diagram, page 4. revised table 4 clock interface, page 10 (ckxtal2 pin revised from i to io).
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix iv track id: jatr-2265-11 rev. 1.4 table of contents 1. general desc ription ............................................................................................................ ..................................1 2. features ....................................................................................................................... ..................................................2 3. applications ................................................................................................................... .............................................3 3.1. a pplication d iagram ...............................................................................................................................................3 4. block diagram .................................................................................................................. .........................................4 5. pin assignments ................................................................................................................ .........................................5 5.1. rtl8201f (32-p in ).....................................................................................................................................................5 5.2. g reen p ackage and v ersion i dentification ........................................................................................................5 5.3. rtl8201fl (48-p in ) ..................................................................................................................................................6 5.4. g reen p ackage and v ersion i dentification ........................................................................................................6 5.5. rtl8201fn (48-p in )..................................................................................................................................................7 5.6. g reen p ackage and v ersion i dentification ........................................................................................................7 6. pin descriptions............................................................................................................... ..........................................8 6.1. mii i nterface ............................................................................................................................................................8 6.2. s erial m anagement i nterface ............................................................................................................................10 6.3. rmii i nterface .......................................................................................................................................................10 6.4. c lock i nterface .....................................................................................................................................................10 6.5. 10m bps /100m bps n etwork i nterface .................................................................................................................11 6.6. t ransmit b ias r eference ............................................................................................................................... .......11 6.7. d evice c onfiguration i nterface ........................................................................................................................11 6.8. p ower and g round p ins ............................................................................................................................... .........13 6.9. r eset and o ther p ins ............................................................................................................................... ..............14 6.10. nc (n ot c onnected ) p ins ............................................................................................................................... .......14 7. register descriptions.......................................................................................................... ...............................15 7.1. r egister 0 b asic m ode c ontrol r egister ..........................................................................................................15 7.2. r egister 1 b asic m ode s tatus r egister .............................................................................................................16 7.3. r egister 2 phy i dentifier r egister 1..................................................................................................................17 7.4. r egister 3 phy i dentifier r egister 2..................................................................................................................17 7.5. r egister 4 a uto -n egotiation a dvertisement r egister (anar) ...................................................................17 7.6. r egister 5 a uto -n egotiation l ink p artner a bility r egister (anlpar)....................................................18 7.7. r egister 6 a uto -n egotiation e xpansion r egister (aner) ............................................................................19 7.8. p age 0 r egister 13 macr (mmd a ccess c ontrol r egister ; a ddress 0 x 0d) ...............................................20 7.9. p age 0 r egister 14 maadr (mmd a ccess a ddress d ata r egister ; a ddress 0 x 0e)...................................20 7.10. r egister 24 p ower s aving m ode r egister (psmr) ...........................................................................................20 7.11. r egister 28 f iber m ode and l oopback r egister ...............................................................................................21 7.12. r egister 30 i nterrupt i ndicators and snr d isplay r egister ........................................................................21 7.13. r egister 31 p age s elect r egister .......................................................................................................................21 7.14. p age 4 r egister 16 eee c apability e nable r egister .......................................................................................22 7.15. p age 4 r egister 21 eee c apability r egister .....................................................................................................22 7.16. p age 7 r egister 16 rmii m ode s etting r egister (rmsr) ................................................................................22 7.17. p age 7 r egister 17 c ustomized led s s etting r egister ...................................................................................23 7.18. p age 7 r egister 18 eee led s e nable r egister .................................................................................................23 7.19. p age 7 r egister 19 i nterrupt , wol e nable , and led s f unction r egisters ................................................24 7.20. p age 7 r egister 20 mii tx i solate r egister ......................................................................................................25 7.21. p age 7 r egister 24 s pread s pectrum c lock r egister ......................................................................................25 7.22. mmd r egister m apping and d efinition .............................................................................................................25 7.22.1. eeepc1r (pcs control 1 register, mmd device 3, ad dress 0x00) .............................................................25
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix v track id: jatr-2265-11 rev. 1.4 7.22.2. eeeps1r (pcs status 1 register, mmd device 3, address 0x01) ................................................................26 7.22.3. eeecr (eee capability register, mmd device 3; address 0x14)................................................................26 7.22.4. eeewer (eee wake error register, mmd device 3; address 0x16) ..........................................................26 7.22.5. eeear (eee advertisement register, mmd device 7; address 0x3c) ..........................................................27 7.22.6. eeelpar (eee link partner ability regist er, mmd device 7; address 0x3d) ............................................27 8. functional description......................................................................................................... ............................28 8.1. mii and m anagement i nterface ..........................................................................................................................29 8.1.1. data tran sitio n ....................................................................................................................................................29 8.1.2. serial manageme nt interface .................................................................................................... ...........................29 8.2. i nterrupt .................................................................................................................................................................31 8.3. a uto -n egotiation and p arallel d etection .....................................................................................................31 8.3.1. setting the medium type and interface mode to mac.............................................................................. ...........31 8.4. led f unctions ........................................................................................................................................................32 8.4.1. led and phy address ............................................................................................................ .............................32 8.4.2. link monitor................................................................................................................... ......................................32 8.4.3. rx led ......................................................................................................................... .......................................33 8.4.4. tx led.................................................................................................................................................................33 8.4.5. tx/rx led...................................................................................................................... .....................................34 8.4.6. link/act led ....................................................................................................................................................34 8.4.7. customized led...................................................................................................................................................35 8.4.8. eee led behavior............................................................................................................... ................................36 8.5. p ower d own and l ink d own p ower s aving m odes ..........................................................................................36 8.6. 10m/100m t ransmit and r eceive .........................................................................................................................37 8.6.1. 100base-tx transmit an d receive operation ...................................................................................... ...............37 8.6.2. 100base-fx fiber transmit and receive op eration ................................................................................ ...........37 8.6.3. 10base-t transmit and receive op eration........................................................................................ ..................37 8.7. r eset and t ransmit b ias ............................................................................................................................... ........38 8.8. 3.3v p ower s upply and v oltage c onversion c ircuit ......................................................................................38 8.9. a utomatic p olarity c orrection ........................................................................................................................39 8.10. f ar e nd f ault i ndication ............................................................................................................................... ......39 8.11. w ake -o n -lan (wol).......................................................................................................................... ..................39 8.11.1. magic packet and wa ke-up frame format.......................................................................................... ..........39 8.11.2. active low wa ke-on-lan......................................................................................................... ......................40 8.11.3. pulse low wa ke-on-lan.......................................................................................................... ......................41 8.11.4. wake-on-lan pin types (mii mode) ............................................................................................... ..............42 8.11.5. wake-on-lan pin types (rmii mode).............................................................................................. .............42 8.12. e nergy e fficient e thernet (eee)........................................................................................................................43 8.13. s pread s pectrum c lock (ssc) .......................................................................................................................... ...43 9. characteristics................................................................................................................ ......................................44 9.1. dc c haracteristics ............................................................................................................................... ................44 9.1.1. absolute maxi mum ratings ....................................................................................................... ...........................44 9.1.2. recommended oper ating conditions ............................................................................................... ....................44 9.1.3. power on and phy reset sequence................................................................................................ .....................45 9.1.4. rmii input mode power dissipation .............................................................................................. .....................46 9.1.5. input volta ge: vcc............................................................................................................. ...................................46 9.2. ac c haracteristics ............................................................................................................................... ................47 9.2.1. mii transmission cycle ti ming .................................................................................................. .........................47 9.2.2. mii reception cycle ti ming..................................................................................................... ............................48 9.2.3. rmii transmission and reception c ycle timing ................................................................................... ..............49 9.2.4. mdc/mdio timing ................................................................................................................ .............................51 9.2.5. transmission w ithout collision ................................................................................................. ...........................52 9.2.6. reception with out error ........................................................................................................ ...............................52 9.3. c rystal c haracteristics ............................................................................................................................... ......53
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix vi track id: jatr-2265-11 rev. 1.4 9.4. o scillator r equirements ............................................................................................................................... .....53 9.5. c lock r equirements ............................................................................................................................... ..............54 9.6. t ransformer c haracteristics ............................................................................................................................54 10. mechanical dimensions.................................................................................................................................55 10.1. rtl8201f (qfn-32) ................................................................................................................................................55 10.2. rtl8201fl (lqfp-48) ............................................................................................................................................56 10.3. rtl8201fn (qfn-48) ....................................................................................................................... ......................57 11. ordering information ........................................................................................................... ........................58 11.1. rtl8201f s eries s election g uide .......................................................................................................................58
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix vii track id: jatr-2265-11 rev. 1.4 list of tables t able 1. mii i nterface ..............................................................................................................................................................8 t able 2. s erial m anagement i nterface ..............................................................................................................................1 0 t able 3. rmii i nterface .........................................................................................................................................................10 t able 4. c lock i nterface .......................................................................................................................................................10 t able 5. 10m bps /100m bps n etwork i nterface ....................................................................................................................11 t able 6. t ransmit b ias r eference ............................................................................................................................... .........11 t able 7. d evice c onfiguration i nterface ...........................................................................................................................11 t able 8. p ower and g round p ins ............................................................................................................................... ...........13 t able 9. r eset and o ther p ins ............................................................................................................................... ................14 t able 10. nc (n ot c onnected ) p ins ............................................................................................................................... .........14 t able 11. r egister 0 b asic m ode c ontrol r egister ............................................................................................................15 t able 12. r egister 1 b asic m ode s tatus r egister ...............................................................................................................16 t able 13. r egister 2 phy i dentifier r egister 1 ...................................................................................................................17 t able 14. r egister 3 phy i dentifier r egister 2 ...................................................................................................................17 t able 15. r egister 4 a uto -n egotiation a dvertisement r egister (anar) .....................................................................17 t able 16. r egister 5 a uto -n egotiation l ink p artner a bility r egister (anlpar)......................................................18 t able 17. r egister 6 a uto -n egotiation e xpansion r egister (aner) ..............................................................................19 t able 18. p age 0 r egister 13 macr (mmd a ccess c ontrol r egister ; a ddress 0 x 0d).................................................20 t able 19. p age 0 r egister 14 maadr (mmd a ccess a ddress d ata r egister ; a ddress 0 x 0e) ....................................20 t able 20. r egister 24 p ower s aving m ode r egister (psmr) .............................................................................................20 t able 21. r egister 28 f iber m ode and l oopback r egister ................................................................................................21 t able 22. r egister 30 i nterrupt i ndicators and snr d isplay r egister ..........................................................................21 t able 23. r egister 31 p age s elect r egister .........................................................................................................................21 t able 24. p age 4 r egister 16 eee c apability e nable r egister ..........................................................................................22 t able 25. p age 4 r egister 21 eee c apability r egister ........................................................................................................22 t able 26. p age 7 r egister 16 rmii m ode s etting r egister (rmsr)...................................................................................22 t able 27. c ustomized led m atrix t able .............................................................................................................................23 t able 28. p age 7 r egister 17 c ustomized led s s etting r egister .....................................................................................23 t able 29. p age 7 r egister 18 eee led s e nable r egister ....................................................................................................23 t able 30. p age 7 r egister 19 i nterrupt , wol e nable , and led s f unction r egisters ...................................................24 t able 31. p age 7 r egister 20 mii tx i solate r egister .........................................................................................................25 t able 32. p age 7 r egister 24 s pread s pectrum c lock r egister ........................................................................................25 t able 33. mmd r egister m apping and d efinition ...............................................................................................................25 t able 34. eeepc1r (pcs c ontrol 1 r egister , mmd d evice 3, a ddress 0 x 00) ................................................................25 t able 35. eeeps1r (pcs s tatus 1 r egister , mmd d evice 3, a ddress 0 x 01)....................................................................26 t able 36. eeecr (eee c apability r egister , mmd d evice 3; a ddress 0 x 14) ...................................................................26 t able 37. eeewer (eee w ake e rror r egister , mmd d evice 3; a ddress 0 x 16).............................................................26 t able 38. eeear (eee a dvertisement r egister , mmd d evice 7; a ddress 0 x 3 c )...........................................................27 t able 39. eeelpar (eee l ink p artner a bility r egister , mmd d evice 7; a ddress 0 x 3 d ) ...........................................27 t able 40. m anagement f rame f ormat ............................................................................................................................... ...29 t able 41. s erial m anagement ............................................................................................................................... .................30 t able 42. s etting the m edium t ype and i nterface m ode to mac....................................................................................31 t able 43. p ower s aving m ode p in s ettings ..........................................................................................................................36 t able 44. w ake -o n -lan p in t ypes (mii m ode ) ....................................................................................................................42 t able 45. w ake -o n -lan p in t ypes (rmii m ode )..................................................................................................................42 t able 46. a bsolute m aximum r atings ............................................................................................................................... ...44 t able 47. r ecommended o perating c onditions ...................................................................................................................44 t able 48. p ower o n and phy r eset s equence ......................................................................................................................45 t able 49. rmii i nput m ode p ower d issipation (w hole s ystem )........................................................................................46 t able 50. i nput v oltage : v cc ............................................................................................................................... ..................46 t able 51. mii t ransmission c ycle t iming .............................................................................................................................48 t able 52. mii r eception c ycle t iming ............................................................................................................................... ....49
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix viii track id: jatr-2265-11 rev. 1.4 t able 53. rmii t ransmission and r eception c ycle t iming ................................................................................................50 t able 54. mdc/mdio t iming ...................................................................................................................................................51 t able 55. c rystal c haracteristics ............................................................................................................................... ........53 t able 56. o scillator r equirements ............................................................................................................................... .......53 t able 57. c lock r equirements ............................................................................................................................... ................54 t able 58. t ransformer c haracteristics ..............................................................................................................................5 4 t able 59. o rdering i nformation ............................................................................................................................... .............58 t able 60. rtl8201f s eries s election g uide .........................................................................................................................58 list of figures f igure 1. a pplication d iagram ................................................................................................................................................3 f igure 2. b lock d iagram ..........................................................................................................................................................4 f igure 3. rtl8201f qfn-32 p in a ssignments ........................................................................................................................5 f igure 4. rtl8201fl lqfp-48 p in a ssignments ....................................................................................................................6 f igure 5. rtl8201fn qfn-48 p in a ssignments .....................................................................................................................7 f igure 6. r ead c ycle ...............................................................................................................................................................30 f igure 7. w rite c ycle .............................................................................................................................................................30 f igure 8. led and phy a ddress c onfiguration ................................................................................................................32 f igure 9. rx led......................................................................................................................................................................33 f igure 10. tx led .....................................................................................................................................................................33 f igure 11. tx/rx led...............................................................................................................................................................34 f igure 12. link/act led ........................................................................................................................................................34 f igure 13. c ustomized led with / without lpi led m ode ...................................................................................................35 f igure 14. eee led b ehavior ..................................................................................................................................................36 f igure 15. a ctive l ow w hen r eceiving a m agic p acket ....................................................................................................40 f igure 16. a ctive l ow w hen r eceiving a w ake -u p f rame .................................................................................................40 f igure 17. p ulse l ow w hen r eceiving a m agic p acket ......................................................................................................41 f igure 18. p ulse l ow w hen r eceiving a w ake -u p f rame ...................................................................................................41 f igure 19. s pectrum s pread c lock ............................................................................................................................... .........43 f igure 20. p ower o n and phy r eset s equence ....................................................................................................................45 f igure 21. mii i nterface s etup /h old t ime d efinitions .......................................................................................................47 f igure 22. mii t ransmission c ycle t iming -1.........................................................................................................................47 f igure 23. mii t ransmission c ycle t iming -2.........................................................................................................................47 f igure 24. mii r eception c ycle t iming -1 ............................................................................................................................. .48 f igure 25. mii r eception c ycle t iming -2 ............................................................................................................................. .48 f igure 26. rmii i nterface s etup , h old t ime , and o utput d elay t ime d efinitions ........................................................49 f igure 27. rmii t ransmission and r eception c ycle t iming ...............................................................................................50 f igure 28. mdc/mdio i nterface s etup , h old t ime , and v alid from mdc r ising e dge t ime d efinitions .................51 f igure 29. mdc/mdio t iming ..................................................................................................................................................51 f igure 30. mac to phy t ransmission without c ollision ..................................................................................................52 f igure 31. phy to mac r eception w ithout e rror .............................................................................................................52
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 1 track id: jatr-2265-11 rev. 1.4 1. general description the RTL8201F-VB-CG, rtl8201fl-vb-cg, and r tl8201fn-vb-cg are single-chip/single-port 10/100mbps ethernet phyceivers that support: ? mii (media independent interface) ? rmii (reduced media i ndependent interface) the rtl8201f/fl/fn implement all 10/100m ethernet physical-layer functions including the physical coding sublayer (pcs), physical me dium attachment (pma), twisted pair physical medium dependent sublayer (tp-pmd), 10base-tx encoder/decoder, and twisted-pair media access unit (tpmau). the rtl8201f/fl/fn support auto mdix. a pecl (pseudo emitter coupled logic) interface is supported to connect with an external 100base-fx fiber optical transceiver. the chip utilizes an advanced cmos pro cess to meet low voltage and low power requirements. with on-chip dsp (digital signal processing ) technology, the chip provides excellent performance unde r all operating conditions. note: version differences are listed in section 11 ordering information, page 58.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 2 track id: jatr-2265-11 rev. 1.4 2. features ? supports ieee 802.3az-2010 (eee) ? 100base-tx ieee 802.3u compliant ? 10base-t ieee 802.3 compliant ? supports mii mode ? supports rmii mode ? full/half duplex operation ? twisted pair or fiber mode output ? supports auto-negotiation ? supports power down mode ? supports link down power saving ? supports base line wander (blw) compensation ? supports auto mdix ? supports interrupt function ? supports wake-on-lan (wol) ? adaptive equalization ? automatic polarity correction ? leds ? rtl8201f and rtl8201fl provide two network status leds ? rtl8201fn provides three network status leds ? supports 25mhz extern al crystal or osc ? supports 50mhz external osc clock input ? provides 50mhz clock source for mac ? low power supply 1.1v and 3.3v; 1.1v is generated by an internal regulator ? 0.11m cmos process ? packages: ? 32-pin mii/rmii qfn green package (rtl8201f) ? 48-pin mii/rmii lqfp green package (rtl8201fl) ? 48-pin mii/rmii qfn green package (rtl8201fn)
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 3 track id: jatr-2265-11 rev. 1.4 3. applications ? dtv (digital tv) ? mau (media access unit) ? cnr (communication and network riser) ? game console ? printer and office machine ? dvd player and recorder ? ethernet hub ? ethernet switch in addition, the rtl8201f/fl/ fn can be used in any embedded system with an ethernet mac that needs a utp physical connection or fiber pecl interface to an external 100base-fx optical transceiver module. 3.1. application diagram rj-45 magnet ic s figure 1. application diagram
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 4 track id: jatr-2265-11 rev. 1.4 4. block diagram rxin+ rxin- txo+ txo- rxc 25m or 50m txc td+ variable current 3 level driver master pll adaptive equalizer 3 level mlt-3 to nrzi serial to parallel ck data slave pll parallel to serial data alignment descrambler scrambler 10/ 100 half /full switch logic 10/100 m auto- negotiation control logic manchester coded waveform 10 m output waveform shaping data recovery receive low pass filter rxd rxc 25m txd txc txd10 txc10 rxd10 rxc10 link pulse 10m 100 m 5b 4b decoder 4b 5b encoder 25m 25m 25m comparator wol pmeb lpi indication (eee capability exchange) (lpi detection) ( lpi generation) supports eee quiet ( amplitude reduction) interface mii/rmii txd rxd figure 2. block diagram
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 5 track id: jatr-2265-11 rev. 1.4 5. pin assignments 5.1. rtl8201f (32-pin) pmeb rset mdi+[0] mdi-[0] rxdv led0/ phyad[0]/ phyrstb mdc mdi+[1] mdi-[1] txd[1] txd[2] txd[3] txen mdi o avdd33 avdd10out figure 3. rtl8201f qfn-32 pin assignments 5.2. green package and version identification green package is indicated by the g in gxxxv (f igure 3). the version is shown in the location marked v.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 6 track id: jatr-2265-11 rev. 1.4 5.3. rtl8201fl (48-pin) mdi+ [0] mdi - [0] mdi+[1] mdi- [1] gnd nc pmeb mdc crs/ cr s_dv dvdd10 gnd txd[2] mdio intb led0 /phyad[0] led1 /phyad[1] nc avdd33 nc txen phyrstb txer txd[3] nc figure 4. rtl8201fl lqfp-48 pin assignments 5.4. green package and version identification green package is indicated by the g in gxxxv (f igure 4). the version is shown in the location marked v.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 7 track id: jatr-2265-11 rev. 1.4 5.5. rtl8201fn (48-pin) figure 5. rtl8201fn qfn-48 pin assignments 5.6. green package and version identification green package is indicated by the g in gxxxv (f igure 5). the version is shown in the location marked v.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 8 track id: jatr-2265-11 rev. 1.4 6. pin descriptions i: input li: latched input during power up or reset o: output io: bi-directional input and output p: power hz: high impedance during power on reset pu: internal pull up during power on reset pd: internal pull down during power on reset od: open drain output 6.1. mii interface table 1. mii interface name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description txc o/pd 15 22 22 transmit clock. this pin provides a continuous clock as a timing reference for txd [3:0] and txen signals. txc is 25mhz in 100mbps mode and 2.5mhz in 10mbps mode. txen i/pd 20 27 27 transmit enable. the input signal indicates the presence of valid nibble data on txd [3:0]. an intern al weakly pulled low resistor prevents the bus floating. txer i/pd - 12 12 transmit error. txd[0] txd[1] txd[2] txd[3] i/pd i/pd i/pd i/pd 16 17 18 19 23 24 25 26 23 24 25 26 transmit data. the mac will source txd [0:3] synchronous with txc when txen is asserted. an internal weakly pulled low resistor prevents the bus floating. rxc o/pd 13 19 19 receive clock. this pin provides a continuous clock reference for rxdv and rxd [0:3] signals. rxc is 25mhz in 100mbps mode and 2.5mhz in 10mbps mode. col o/pd 27 38 38 collision detect. col is asserted high when a collision is detected on the media. crs/ crs_dv o/pd 26 36 36 carrier sense. this pins signal is asserted high if the media is not in idle state.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 9 track id: jatr-2265-11 rev. 1.4 name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description rxdv li/o/pd 8 13 13 receive data valid. this pins signal is asserted high when received data is present on the rxd[3:0] lines. the signal is de-asserted at the end of the packet. the sign al is valid on the rising edge of the rxc. this pin should be pulled low when operating in mii mode. 0: mii mode 1: rmii mode an internal weakly pulled low resistor sets this to the default of mii mode. it is possible to use an external 4.7k ? pulled high resistor to enable rmii mode. after power on, the pin operates as the receive data valid pin. rxd[0] rxd[1] rxd[2] rxd[2]/ intb o/pd li/o/pd o/pd o/pd 9 10 - 11 14 16 17 - 14 16 17 - receive data. these are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the rxc for reception by the extern al physical unit (phy). note 1: an internal weakly pulled low resistor sets rxd[1] to the led function (default). use an external 4.7k ? pulled high resistor to enable the wol function for the rtl8201f. note 2: the rtl8201f pin11 is named rxd[2]/intb. when in rmii mode, this pin is used for the interrupt function. see table 9, page 14 for intb descriptions. rxd[3]/ clk_ctl li/o/pd 12 18 18 receive data. this is the parallel receive data line aligned on the nibble boundaries driven synchronou sly to the rxc for reception by the external physical unit (phy). rxd[3]/clk_ctl pin is the hardware strap in rmii mode. 1: ref_clk input mode 0: ref_clk output mode note: an internal weakly pulled low resistor sets rxd[3]/clk_ctl to ref_clk output mode (default). rxer/ fxen li/o/pd 28 39 39 receive error. if a 5b decode error occurs, such as invalid /j/k/, invalid /t/r/, or invalid symbol, this pin will go high. fiber/utp enable. this pins status is latched at power on reset to determine the media mode to operate in. 1: fiber mode 0: utp mode an internal weakly pulled low resistor sets this to the default of utp mode. it is possible to use an external 4.7k ? pulled high resistor to enable fiber mode. after power on, the pin operates as the receive error pin.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 10 track id: jatr-2265-11 rev. 1.4 6.2. serial management interface table 2. serial management interface name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description mdc i/pu 22 30 30 management data clock. this pin provides a clock synchronous to mdio, which may be asynchronous to the transmit txc and receive rxc clocks. the clock rate can be up to 2.5mhz. use an internal weakly pulled high resistor to prevent the bus floating. mdio io/pu 23 31 31 management data input/output. this pin provides the bi-directional signal used to transfer management information. 6.3. rmii interface table 3. rmii interface name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description txc io/pd 15 22 22 synchronous 50mhz clock reference for receive, transmit, and control interfa ce. the direction is decided by page 7, register 16. the default direction is reference clock output mode if rxd[3]/clk_ctl pin floating. crs/ crs_dv o/pd 26 36 36 carrier sense/receive data valid. crs_dv shall be asserted by the phy when the receive medium is non-idle. txen i/pd 20 27 27 transmit enable. txd[0:1] i/pd 16, 17 23, 24 23, 24 transmit data. rxd[0:1] o/pd 9, 10 14 , 16 14, 16 receive data. rxer/ fxen li/o/pd 28 39 39 receive error. rx_er is a required output of the phy, but is an optional input for the mac. 6.4. clock interface table 4. clock interface name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description ckxtal2 io 32 43 43 25mhz crystal output. this pin provides the 25mhz crystal output. if an external 25mhz/50mhz oscillator or clock is used, connect ckxtal2 to the oscillator or clock output (see section 9.4 oscillator requirements, page 53). ckxtal1 i 31 42 42 25mhz crystal input. this pin provides the 25mhz crystal input. must be shorted to gnd when an external 25mhz/50mhz oscillator or clock drives ckxtal2.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 11 track id: jatr-2265-11 rev. 1.4 6.5. 10mbps/100mbps network interface table 5. 10mbps/100mbps network interface name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description mdi+[0] mdi-[0] io 3 4 1 2 1 2 transmit output. differential transmit output pa ir shared by 100base-tx, 100base-fx, and 10base-t modes. when configured as 100base-tx, output is an mlt-3 encoded waveform. when configured as 100base-fx, the output is pseudo- ecl level. mdi+[1] mdi-[1] io 5 6 4 5 4 5 receive input. differential receive input pair shared by 100base-tx, 100base-fx, and 10base-t modes. 6.6. transmit bias reference table 6. transmit bias reference name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description rset i 1 46 46 transmit bias resistor connection. this pin should be pulled to gnd by a 2.49k ? (1%) resistor to define driving current for the transmit dac. 6.7. device configuration interface table 7. device configuration interface name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description rxdv li/o/pd 8 13 13 receive data valid. this pins signal is asserted high when received data is present on the rxd [3:0] lines. the signal is de-asserted at the end of the packet. the signal is valid on the rising edge of the rxc. this pin should be pulled low when operating in mii mode. 0: mii mode 1: rmii mode an internal weakly pulled low resistor sets this to the default of mii mode. it is possible to use an external 4.7k ? pulled high resistor to enable rmii mode. after power on, the pin operates as the receive data valid pin. rxd[1] li/o/pd 10 16 16 an internal weakly pulled low resistor sets rxd[1] to the led function (default). use an external 4.7k ? pulled high resistor to enable the wol function for the rtl8201f.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 12 track id: jatr-2265-11 rev. 1.4 name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description led0/ phyad[0] led0/ phyad[0]/ pmeb led1/ phyad[1] led2/ phyad[2] li/o/pu li/o/pu li/o/pd li/o/pd - 24 25 - 34 - 35 - 34 - 35 32 phy address and customized led settings. the default available phy addresses are: rtl8201f: 00000~00011. rtl8201fl: 00100~00111 (when pmeb pin is pulled high) 00000~00011 (when pmeb pin is pulled low) rtl8201fn: 00000~00111. traditional led function selection led _sel 00 01 10 11 led0 act all link all / act all link 10 / act all link 10 /act 10 led1 link 100 link 100 link 100 link 100 / act 100 led2 reserved reserved reserved reserved note 1: for customized led settings, see section 7.17, page 23. note 2: led_sel default is 11. refer to section 7.19, page 24. an internal weakly pulled low resistor sets rxd[1] to the led function for rtl8201f (default). use an external 4.7k ? pulled high resistor to enable the wol function for rtl8201f. traditional led function selection for the rtl8201f with wol enabled with the rtl8201f wol function enabled, the phy address must be 00001 or 00011. led _sel 00 01 10 11 led1 link 100 link 100 link 100 link 100 / act 100 rxd[3]/ clk_ctl li/o/pd 12 18 18 receive data. this is the parallel receive data line aligned on the nibble boundaries driven synchronou sly to the rxc for reception by the external physical unit (phy). rxd [3]/clk_ctl pin is the hardware strap in rmii mode. 1: ref_clk input mode 0: ref_clk output mode note: an internal weakly pulled low resistor sets rxd[3]/clk_ctl to ref_clk output mode (default).
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 13 track id: jatr-2265-11 rev. 1.4 name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description rxer/ fxen li/o/pd 28 39 39 fiber/utp interface. this pins status is latched at power on reset to determine the media mode to operate in. 1: fiber mode 0: utp mode an internal weakly pulled low resistor sets this to the default of utp mode. it is possible to use an external 4.7k ? pulled high resistor to enable fiber mode. en_ldo_ out li/o/pu - - 11 ldo mode strap. 1: ldo enable 2: ldo disable 6.8. power and ground pins table 8. power and ground pins name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description avdd33 p 7, 30 6, 41 6, 41 3.3v analog power input. 3.3v power supply for analog circuit; should be well decoupled. dvdd33 p 14 15, 21, 37 15, 21, 37 3.3v digital power input. 3.3v power supply for digital circuit. dvdd10 p - 28 28 1.1v digital power. avdd10out o 2 48 48 power output. be sure to connect a 0.1f ceramic capacitor for decoupling purposes. the connection method is outlined in section 8.8 3.3v power supply and voltage conversion circuit, page 38. dvdd10out o 29 40 40 power output. be sure to connect a 0.1f ceramic capacitor for decoupling purposes. the connection method is outlined in section 8.8 3.3v power supply and voltage conversion circuit, page 38. gnd p e-pad 7, 20, 33, 47 e-pad ground. should be conn ected to a larger gnd plane. exposed pad (e-pad) is analog and digital ground.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 14 track id: jatr-2265-11 rev. 1.4 6.9. reset and other pins table 9. reset and other pins name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description phyrstb i/hz 21 29 29 resetb. set low to reset the chip. for a complete reset, this pin must be asserted low for at least 10ms. note: when the wol function is enabled, keep the pin high (rtl8201fn only). intb o/od - 32 20 interrupt. set low if link status changed, duplex changed, or auto negotiation failed. active low. this pin is an open-drain design, and for default value should be pulled high by an external 4.7k ? . if not used, keep floating. rxd[2]/intb o/pd 11 - - interrupt. set low if link status changed, duplex changed, or auto negotiation failed. active low. this pin is an open-drain design, and for default value should be pulled high by an external 4.7k ? . if not used, keep floating. note: this pin is used for the interrupt function only when in the rmii mode. pmeb o/od 24 10 33 power management enable. set low if received a magic packet or wake up frame; active low. 6.10. nc (not connected) pins table 10. nc (not connected) pins name type pin no. (8201f) pin no. (8201fl) pin no. (8201fn) description nc - - 3, 8, 9, 11, 44, 45 3, 7, 8, 9, 10, 44, 45, 47 not connected.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 15 track id: jatr-2265-11 rev. 1.4 7. register descriptions this section describes the functions and usage of the registers available in this file. in this section the following abbreviations are used. rw: read/write rw/efus: read/write/efuse burnable ro: read only rw/li: read/write/latch in rc: read clear rw/sc: read/write/self-clearing sc: self-clear note: rw/efus and rw/li types will return to default va lues after a software reset (set reg.0 bit15 to 1). 7.1. register 0 basic mode control register table 11. register 0 basic mode control register address name description mode default 0:15 reset this bit sets the status and control registers of the phy in the default state. this bit is self-clearing. 1: software reset 0: normal operation register 0 and register 1 will return to default values after a software reset (set bit15 to 1). this action may change the internal phy state and the state of the physical link associated with the phy. rw/ sc 0 0:14 loopback this bit enables loopback of transmit data nibbles txd3:0 to the receive data path. 1: enable loopback 0: normal operation rw 0 0:13 speed selection this bit sets the network speed. 1: 100mbps 0: 10mbps after completing auto negotiation, this bit will reflect the speed status. 1: 100base-t 0: 10base-t when 100base-fx mode is enabled, this bit=1 and is read only. rw 1 0:12 auto negotiation enable this bit enables/disables the nway auto-negotiation function. 1: enable auto-negotiation; bits 0:13 and 0:8 will be ignored 0: disable auto-negotiation; bits 0:13 and 0:8 will determine the link speed and the data transfer mode, respectively when 100base-fx mode is enabled, this bit=0 and is read only. rw 1 0:11 power down this bit turns down the power of the phy chip, including the internal crystal oscillator circuit. the mdc, mdio is still a live for accessing the mac. 1: power down 0: normal operation rw 0 0:10 isolate 1: electrically isolate the ph y from mii/gmii/rgmii/rsgmii. phy is still able to respond to mdc/mdio. 0: normal operation rw 0
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 16 track id: jatr-2265-11 rev. 1.4 address name description mode default 0:9 restart auto negotiation this bit allows the nway auto-negotiation function to be reset. 1: re-start auto-negotiation 0: normal operation rw/ sc 0 0:8 duplex mode this bit sets the duplex mode if auto-negotiation is disabled (bit 0:12=0). 1: full duplex 0: half duplex after completing auto-negotiation, this bit will reflect the duplex status. 1: full duplex 0: half duplex rw 1 0:7 collision test collision test. 1: collision test enabled 0: normal operation when set, this bit will cause the col signal to be asserted in response to the txen assertion within 512-bit times. the col signal will be de-asserted within 4-bit times in response to the txen de-assertion. rw 0 0:6 speed selection[1] speed select bit 1. refer to bit 0.13. rw 0 0:5~0 reserved reserved. - - 7.2. register 1 basic mode status register table 12. register 1 basic mode status register address name description mode default 1:15 100base-t4 1: enable 100base-t4 support 0: suppress 100base-t4 support ro 0 1:14 100base_tx_fd 1: enable 100base-tx full duplex support 0: suppress 100base-tx full duplex support ro 1 1:13 100base_tx_hd 1: enable 100base-tx half duplex support 0: suppress 100base-tx half duplex support ro 1 1:12 10base_t_fd 1: enable 10base-t full duplex support 0: suppress 10base-t full duplex support ro 1 1:11 10_base_t_hd 1: enable 10base-t half duplex support 0: suppress 10base-t half duplex support ro 1 1:10~7 reserved reserved. - - 1:6 mf preamble suppression the rtl8201f/fl/fn will accept management frames with preamble suppressed. a minimum of 32 preamble bits are required for the first management interface read/write transaction after reset. one idle bit is required between any two management transactions as per ieee 802.3u specifications. ro 1 1:5 auto negotiation complete 1: auto-negotiation process completed 0: auto-negotiation process not completed ro 0 1:4 remote fault 1: remote fault condition detected (cleared on read) 0: no remote fault condition detected when in 100base-fx mode, this bit means an in-band signal far-end-fault has been detected (see 8.10 far end fault indication, page 39). rc 0
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 17 track id: jatr-2265-11 rev. 1.4 address name description mode default 1:3 auto-negotiation ability 1: phy is able to perform auto-negotiation 0: phy is not able to perform auto-negotiation ro 1 1:2 link status 1: valid link established 0: no valid link established this bit indicates whether the link was lost since the last read. for the current link status, read this register twice. ro 0 1:1 jabber detect 1: jabber condition detected 0: no jabber condition detected ro 0 1:0 extended capability 1: extended register capable (permanently=1) 0: not extended register capable ro 1 7.3. register 2 phy identifier register 1 table 13. register 2 phy identifier register 1 address name description mode default 2:15~0 oui composed of the 6 th to 21 st bits of the organizationally unique identifier (oui), respectively. ro 001ch 7.4. register 3 phy identifier register 2 table 14. register 3 phy identifier register 2 address name description mode default 3:15~10 oui_lsb assigned to the 0 through 5 th bits of the oui. ro 110010 3:9~4 model number model number ro 000001 3:3~0 revision number revision number ro 0110 7.5. register 4 auto-negotiation advertisement register (anar) this register contains the advertised abilities of this device as they wi ll be transmitted to its link partner during auto-negotiation. table 15. register 4 auto-negotia tion advertisement register (anar) address name description mode default 4:15 next page next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page rw 0 4:14 acknowledge 1: acknowledge reception of link partner capability data word 0: do not acknowledge reception ro 0 4:13 remote fault 1: advertise remote fault detection capability 0: do not advertise remote fault detection capability rw 0 4:12 reserved reserved. - - 4:11 asymmetric pause 1: advertise asymmetric pause support 0: no support of asymmetric pause rw 0 4:10 pause reserved. rw 0
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 18 track id: jatr-2265-11 rev. 1.4 address name description mode default 4:9 100base-t4 1: 100base-t4 is supported by local node 0: 100base-t4 not supported by local node ro 0 4:8 100base-tx-fd 1: 100base-tx full duplex is supported by local node 0: 100base-tx full duplex not supported by local node rw 1 4:7 100base-tx 1: 100base-tx is supported by local node 0: 100base-tx not supported by local node rw 1 4:6 10base-t-fd 1: 10base-t full duplex supported by local node 0: 10base-t full duplex not supported by local node rw 1 4:5 10base-t 1: 10base-t is supported by local node 0: 10base-t not supported by local node rw 1 4:4~0 selector field binary encoded selector supported by this node. currently only csma/cd 00001 is specified. no other protocols are supported. ro 00001 7.6. register 5 auto-negotiation link partner ability register (anlpar) this register contains the advertised abilities of th e link partner as received dur ing auto-negotiation. the content changes after a successful auto-n egotiation if next-p ages are supported. table 16. register 5 auto -negotiation link partner ability register (anlpar) address name description mode default 5:15 next page next page bit. 0: transmitting the primary capability data page 1: transmitting the protocol specific data page ro 0 5:14 acknowledge 1: link partner acknowledges reception of local nodes capability data word 0: no acknowledgement ro 0 5:13 remote fault 1: link partner is indicating a remote fault 0: link partner is not indicating a remote fault ro 0 5:12 reserved reserved. - - 5:11 asymmetric pause 1: asymmetric flow control supported by link partner 0: no asymmetric flow control supported by link partner when auto-negotiation is enabled, this bit reflects link partner ability. ro 0 5:10 pause 1: flow control supported by link partner 0: no flow control supported by link partner when auto-negotiation is enabled, this bit reflects link partner ability (read only). ro 0 5:9 100base-t4 1: 100base-t4 is supported by link partner 0: 100base-t4 not supported by link partner ro 0 5:8 100base-tx-fd 1: 100base-tx full duplex is supported by link partner 0: 100base-tx full duplex not supported by link partner ro 0
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 19 track id: jatr-2265-11 rev. 1.4 address name description mode default 5:7 100base-tx 1: 100base-tx is supported by link partner 0: 100base-tx not supported by link partner this bit will also be set if the link in 100base-tx is established by parallel detection. ro 0 5:6 10base-t-fd 1: 10base-t full duplex is supported by link partner 0: 10base-t full duplex not supported by link partner ro 0 5:5 10base-t 1: 10base-t is supported by link partner 0: 10base-t not supported by link partner this bit will also be set if the link in 10base-t is established by parallel detection. ro 0 5:4~0 selector field link partners binary encoded node selector. currently only csma/cd 00001 is specified. ro 00001 7.7. register 6 auto-negotiation expansion register (aner) this register contains additional status for nway auto-negotiation. table 17. register 6 auto-negotiation expansion register (aner) address name description mode default 6:15~5 reserved reserved. - - 6:4 parallel detection fault 1: a fault has been detected via the parallel detection function 0: no fault has been detected via the parallel detection function rc 0 6:3 link partner next page ability 1: link partner is next page able 0: link partner is not next page able ro 0 6:2 local next page ability 1: next page is able 0: not next page able ro 0 6:1 page received 1: a new page has been received 0: a new page has not been received rc 0 6:0 link partner auto-negotiation ability if auto-negotiation is enabled, this bit means: 1: link partner is auto-negotiation able 0: link partner is not auto-negotiation able ro 0
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 20 track id: jatr-2265-11 rev. 1.4 7.8. page 0 register 13 macr (mmd access control register; address 0x0d) table 18. page 0 register 13 macr (mmd access control register; address 0x0d) bit name rw default description 13.15:14 function wo 0 00: address 01: data; no post increment 10: data; post increment on reads and writes 11: data; post increment on writes only 13.13:5 rsvd ro 000000000 reserved. 13.4:0 devad wo 0 device address. note 1: used in conjunction with the maadr (regis ter 14) to provide access to the mmd address space. note 2: if the access of maadr is for address (function=00) then it is directed to the address register within the mmd associated with the value in the devad field. note 3: if the access of maadr is for data (function=00) then both the devad field and the mmd address register direct the maadr data accesses to the appropriate registers within the mmd. 7.9. page 0 register 14 maadr (mmd access address data register; address 0x0e) table 19. page 0 register 14 maadr (mmd ac cess address data register; address 0x0e) bit name rw default description 14.15:0 address data rw 0x0000 13.15:14=00 ? mmd devads address register 13.15:14=01, 10, or 11 ? mmd devads data register as indicated by the contents of its address register note: used in conjunction with the macr (register 13) to provide access to the mmd address space. 7.10. register 24 power saving mode register (psmr) table 20. register 24 power saving mode register (psmr) address name description mode default 24:15 enpwrsave enable power saving mode. the bit will return to default value by software reset. rw 1 24:14~0 reserved reserved. - - note: if the ref_clk output is needed in rmii output mo de, ldps (link down power sa ving) must be disabled (see table 43, page 36).
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 21 track id: jatr-2265-11 rev. 1.4 7.11. register 28 fiber mode and loopback register table 21. register 28 fiber mode and loopback register address name description mode default 28:15~6 reserved reserved. - - 28:5 fxmode enable fiber mode. rw 0 28:4~3 reserved reserved. - - 28:2 en_automdix enable auto mdix function. rw 1 28:1 force_mdi force mdi/mdix mode. if enable auto mdix function is disabled: 1: force mdi 0: force mdix rw 1 28:0 reserved reserved. - - 7.12. register 30 interrupt indicators and snr display register table 22. register 30 interrupt indicators and snr display register address name description mode default 30:15 anerr auto-negotiation error interrupt. 1: enable 0: disable rc 0 30:14 spdchg speed mode change interrupt. 1: enable 0: disable rc 0 30:13 duplexchg duplex mode change interrupt. 1: enable 0: disable rc 0 30:12 reserved reserved. - - 30:11 linkstatuschg link status change interrupt. 1: enable 0: disable rc 0 30:10~4 reserved reserved. - - 30:3~0 snr_o these 4-bits show the si gnal to noise ratio value. ro 0000 7.13. register 31 page select register table 23. register 31 page select register address name description mode default 31:15~8 reserved reserved for internal testing. - - 31:7~0 page sel select page address: 00000000~11111111. rw 00000000
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 22 track id: jatr-2265-11 rev. 1.4 7.14. page 4 register 16 eee capability enable register table 24. page4 register 16 eee capability enable register address name description mode default 16:15~14 reserved reserved. - - 16:13 eee_10_cap enable eee 10m capability. rw 1 16:12 eee_nway_en enable next page exchange in nway for eee 100m. rw/ efus 1 16:11~10 reserved reserved. - - 16:9 tx_quiet_en enable ability to turn off power 100tx when tx in quiet state. this bit is recommended to be set to 1 when eee is enabled. rw/ efus 1 16:8 rx_quiet_en enable ability to turn off power 100rx when rx in quiet state. this bit is recommended to be set to 1 when eee is enabled. rw/ efus 1 16:7:0 reserved reserved. - - 7.15. page 4 register 21 eee capability register table 25. page4 register 21 eee capability register address name description mode default 21:15~13 reserved reserved. - - 21:12 rg_dis_ldvt set to 1 to disable the line driver of the analog circuit. rw 0 21:11~1 reserved reserved. - - 21:0 eee_100_cap nway result to indicate link partner supports eee 100m. ro 0 7.16. page 7 register 16 rmii mode setting register (rmsr) table 26. page7 register 16 rmii mode setting register (rmsr) address name description mode default 16:15~13 reserved reserved. - - 16:12 rg_rmii_clkdir this bit sets the type of txc in rmii mode. 0: output 1: input rw/li 0 16:11~8 rg_rmii_tx_offse t adjust rmii tx interface timing. rw/efus 1111 16:7~4 rg_rmii_rx_offset adjust rmii rx interface timing. rw/efus 1111 16:3 rmii mode 0: mii mode 1: rmii mode rw/li 0 16:2 rg_rmii_rxdv_sel 0: crs/crs_dv pin is crs_dv signal 1: crs/crs_dv pin is rxdv signal rw/efus 0 16:1 rg_rmii_rxdsel 0: rmii data only 1: rmii data with ssd error rw/efus 1 16:0 reserved reserved. - - note: set page7, register 16 to 7ffb when an external clock (25mhz and 50mhz) inputs to the c kxtal2 pin.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 23 track id: jatr-2265-11 rev. 1.4 7.17. page 7 register 17 customized leds setting register this register is for setting customized leds. table 27 shows the customized led matrix table. table 27. customized led matrix table link act 10m 100m led0 bit0 bit1 bit3 led1 bit4 bit5 bit7 led2 bit8 bit9 bit11 led pin act=0 act=1 link=0 floating all speed act link>0 selected speed link selected speed link+act note: the rtl8201f/fl only supports led0 and led1. the rtl8201fn supports led0, le d1, and led2. table 28. page7 register 17 customized leds setting register address name description mode default 17:15~12 reserved reserved. - - 17:11~8 led_sel2 customized led2 setting. set bit3 (page7 register 19; table 30, page 24) to 1 to enable customized led function. rw/ efus 0000 17:7~4 led_sel1 customized led1 setting. set bit3 (page7 register 19; table 30, page 24) to 1 to enable customized led function. rw/ efus 0000 17:3~0 led_sel0 customized led0 setting. set bit3 (page7 register 19; table 30, page 24) to 1 to enable customized led function. rw/ efus 0000 7.18. page 7 register 18 eee leds enable register table 29. page7 register 18 eee leds enable register address name description mode default 18:15~3 reserved reserved. - - 18:2 eee_led_en2 enable led2 in eee/lpi mode. rw 0 18:1 eee_led_en1 enable led1 in eee/lpi mode. rw 0 18:0 eee_led_en0 enable led0 in eee/lpi mode. rw 0
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 24 track id: jatr-2265-11 rev. 1.4 7.19. page 7 register 19 interrupt, wol enable, and leds function registers table 30. page7 register 19 interrupt, wol enable, and leds function registers address name description mode default 19:15~14 reserved reserved. - - 19:13 int_linkchg link change interrupt mask. 1: interrupt pin enable 0: interrupt pin disable this bit set to 0 only masks the link change interrupt event in the intb pin. reg30 bit11 always re flects the link change interrupt behavior (see table 22, page 21). rw 0 19:12 int_dupchg duplex change interrupt mask. 1: interrupt pin enable 0: interrupt pin disable this bit set to 0 only masks the duplex change interrupt event in the intb pin. reg30 bit13 always reflects the duplex change interrupt behavior (see table 22, page 21). rw 0 19:11 int_anerr nway error interrupt mask. 1: interrupt pin enable 0: interrupt pin disable this bit set to 0 only masks the nway error interrupt event in the intb pin.reg30 bit15 always re flects the nway error interrupt behavior (see table 22, page 21). rw 0 19:10 rg_led0_wol_sel led and wake-on-lan function selection (rtl8201f only). 1: wake-on-lan function enable 0: led function enable an internal weakly pulled low resistor sets rxd[1] to the led function (default). use an external 4.7k ? pulled high resistor to enable the wol functio n for the rtl8201f. rw/li 0 19:9~6 reserved reserved. - - 19:5~4 led_sel[1:0] traditional led function selection. led_sel 00 01 10 11 led0 act all link all / act all link 10 / act all link 10 /act 10 led1 link 100 link 100 link 100 link 100 /a ct 100 led2 reserved reserved reserved reserved rw/ efus 11 19:3 customized_led customized led enable. 1: customized led function enable 0: customized led function disable see the section 8.4.7 customized led, page 35 for detail. rw/ efus 0 19:2~1 reserved reserved. - - 19:0 en10mlpi enable 10m lpi led function. rw 0
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 25 track id: jatr-2265-11 rev. 1.4 7.20. page 7 register 20 mii tx isolate register table 31. page7 register 20 mii tx isolate register address name description mode default 20:15 rg_tx_isolate_en isolate mii tx path signals when tx idle. rw 0 20:14~0 reserved reserved. - - 7.21. page 7 register 24 spread spectrum clock register table 32. page7 register 24 spread spectrum clock register address name description mode default 24:15~1 reserved reserved. - - 24:0 rg_dis_ssc 0: ssc function is enabled 1: ssc function is disabled rw 0 7.22. mmd register mapping and definition note: mmd registers are placed at page 0 register 13 and register 14. table 33. mmd register mapping and definition device offset access name description 3 0 rw eeepc1r eee pcs control 1 register 3 1 ro/ro, lh eeeps1r eee pcs status control 1 register 3 20 ro eeecr eee capability register 3 22 rc eeewer eee wake error register 7 60 rw eeear eee advertisement register 7 61 ro eeelpar eee link partner ability register note: lh: latching high. 7.22.1. eeepc1r (pcs control 1 register , mmd device 3, address 0x00) table 34. eeepc1r (pcs control 1 regi ster, mmd device 3, address 0x00) bit name rw default description 3.0.15:11 rsvd rw 0 reserved. 3.0.10 clock stop enable rw 0 1: phy stops rxc in lpi 0: rxc not stoppable 3.0.9:0 rsvd rw 0 reserved.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 26 track id: jatr-2265-11 rev. 1.4 7.22.2. eeeps1r (pcs status 1 register, mmd device 3, address 0x01) table 35. eeeps1r (pcs status 1 regi ster, mmd device 3, address 0x01) bit name rw default description 3.1.15:12 rsvd ro 0 reserved. 3.1.11 tx lpi received ro, lh 0 1: tx pcs has received lpi 0: lpi not received 3.1.10 rx lpi received ro, lh 0 1: rx pcs has received lpi 0: lpi not received 3.1.9 tx lpi indication ro 0 1: tx pcs is currently receiving lpi 0: tx pcs is not currently receiving lpi 3.1.8 rx lpi indi cation ro 0 1: rx pcs is currently receiving lpi 0: rx pcs is not currently receiving lpi 3.1.7 rsvd ro 0 reserved. 3.1.6 clock stop capable ro 1 1: mac stops txc in lpi 0: txc not stoppable 3.1.5:0 rsvd ro 0 reserved. 7.22.3. eeecr (eee capability register, mmd device 3; address 0x14) table 36. eeecr (eee capability register, mmd device 3; address 0x14) bit name rw default description 3.20.15:2 rsvd ro 0 reserved. 3.20.1 100base-tx eee ro 1 1: eee is supported for 100base-tx eee 0: eee is not supported for 100base-tx eee 3.20.0 rsvd ro 1 reserved. 7.22.4. eeewer (eee wake error register, mmd device 3; address 0x16) table 37. eeewer (eee wake error re gister, mmd device 3; address 0x16) bit name rw default description 3.22.15:0 eee wake error counter rc 0 used by phy types that support eee to count wake time faults where the phy fails to complete its normal wake sequence within the time required for the specific phy type.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 27 track id: jatr-2265-11 rev. 1.4 7.22.5. eeear (eee advertisement re gister, mmd device 7; address 0x3c) table 38. eeear (eee advertisement register, mmd device 7; address 0x3c) bit name rw default description 7.60.15:3 rsvd rw 0 reserved. 7.60.1 100base-tx eee rw 1 advertise 100base-tx eee capability. 1: advertise 0: do not advertise 7.60.0 rsvd rw 0 reserved. 7.22.6. eeelpar (eee link partner ability register, mmd device 7; address 0x3d) table 39. eeelpar (eee link partner ability register, mmd device 7; address 0x3d) bit name rw default description 7.61.15:3 rsvd ro 0 reserved. 7.61.1 lp 100base-tx eee ro 0 1: link partner is capable of 100base-tx eee 0: link partner is not capable of 100base-tx eee 7.61.0 rsvd ro 0 reserved.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 28 track id: jatr-2265-11 rev. 1.4 8. functional description the rtl8201f/fl/fn phyceiver is a physical layer device that integrates 10base-t and 100base-tx/100base-fx functions, and some extra pow er management features . this device supports the following functions: ? mii interface with mdc/mdio management interface to communicate with the mac ? ieee 802.3u clause 28 auto-negotiation ability ? speed, duplex, auto-negotiati on ability configurable by hard wire or mdc/mdio ? power down mode support ? 4b/5b transform ? scrambling/de-scrambling ? nrz to nrzi, nrzi to mlt-3 ? manchester encode and d ecode for 10base-t operation ? clock and data recovery ? adaptive equalization ? automatic polarity correction ? far end fault indication (fefi) in fiber mode ? network status leds ? wake-on-lan (wol) ? energy efficient ethernet (eee) ? spread spectrum clock (ssc) for rmii ref_clk output mode
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 29 track id: jatr-2265-11 rev. 1.4 8.1. mii and management interface 8.1.1. data transition the mii (media independent interf ace) is an 18-signal interface (as described in ieee 802.3u) supplying a standard interface between the phy and mac layer. this interface operates at two frequencies; 25m hz and 2.5mhz, to support 100mbps/10mbps bandwidth for both transmit and receive functions. transmission the mac asserts the txen signal. it then changes byt e data into 4-bit nibbles and passes them to the phy via txd[3:0]. the phy will sample txd[3:0] s ynchronously with txc C the transmit clock signal supplied by the phy C during the interval txen is asserted. reception the phy asserts the rxdv signal. it passes the rece ived nibble data rxd[3:0] clocked by rxc. crs and col signals are used for collision detection and handling. in 100base-tx mode, when the decode d signal in 5b is not idle, the crs signal will assert. when 5b is recognized as idle it will be de-asserted. in 10bas e-t mode, crs will assert when the 10m preamble has been confirmed and will be de-asserted when the idle pattern has been confirmed. the rxdv signal will be asserted when decoded 5b are /j/k/ and will be de-asserted if the 5b are /t/r/ or idle in 100mbps mode. in 10mbps mode, the rxdv signal is the same as the crs signal. the rxer (receive error) signa l will be asserted if a ny 5b decode errors occur, e.g., an invalid j/k, invalid t/r, or invalid symbol. this pin will go high for one or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame. 8.1.2. serial management interface the mac layer device can use the mdc/mdio mana gement interface to control a maximum of 4 (rtl8201f/fl) or 8 (rtl8201fn) devices, configured with different phy addresses (00b to 11b for the rtl8201f/fl; 000b to 111b for the rtl8201fn). fram es transmitted on the mdc/mdio management interface should have the frame structure shown in table 40. table 40. management frame format management frame fields preamble st op phyad regad ta data idle read 11 01 10 aaaaa rrrrr z0 ddddddd ddddddddd z write 11 01 01 aaaaa rrrrr 10 ddddddd ddddddddd z during a hardware reset, the logic levels of pi ns 34/24, 35/25, and 32/22 (onl y rtl8201fn) are latched to be set as the phy address for management communi cation via the serial interf ace. the read and write frame structure for the management interface is illustrated in figure 6 and figure 7, page 30.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 30 track id: jatr-2265-11 rev. 1.4 figure 6. read cycle 0 1 0 0000 00000 0000 00 0 00000 1 1 111 z write op (code) phy address 0x01 reg. address 0x00(bmcr) turn around reg. data 0x 1340 idle 1 1 z 0 start mdc mdio(mac) pre 1...1 figure 7. write cycle table 41. serial management name description preamble 32 contiguous logical 1s sent by the mac on mdio, along with 32 corresponding cycl es on mdc. this provides synchronization for the phy. st start of frame. indicated by a 01 pattern. op operation code. read: 10 write: 01 phyad phy address. up to 4 phys can be connected to one mac. this 2-bit field selects wh ich phy the frame is directed to. regad register address. this is a 5-bit field that sets which of the 32 registers of the phy th is operation refers to. ta turnaround. this is a 2-bit-time spacing between the register addr ess and the data field of a frame to avoid contention during a read transaction. for a read transaction, both the sta and the phy remain in a high-impedance state for the first bit time of the turnaround. the phy drives a zero bit during the second bit time of the turnaround of a read transaction. data data. these are the 16 bits of data. idle idle condition. not truly part of the management frame. this is a high impedance state. electrically, the phys pull-u p resistor will pull the mdio line to a logical 1.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 31 track id: jatr-2265-11 rev. 1.4 8.2. interrupt whenever there is a status change on the media detected by the r tl8201f/fl/fn, they will drive the interrupt pin (intb) low to issue an interrupt event. the mac senses the status change and accesses the page0 register30 through the mdc/mdio interface in response. once these status registers page0 register30 have been read by the mac through the mdc/mdio, the intb is de-asserted. the rtl8201fn/fl interrupt function removes the need for continuous polling through the mdc/mdio ma nagement interface. note 1: the rtl8201f rxd[2]/intb pin (pin11) is used for the interrupt functi on only when in the rmii mode. note 2: the interrupt function is disabled by defau lt. to enable this function, refer to table 30, page 24 (page7 register 19 bit[13:11]). 8.3. auto-negotiation and parallel detection the rtl8201f/fl/fn supports ieee 802.3u clause 28 auto-negotiation for operation with other transceivers supporting auto-negotiation. the rtl 8201f/fl/fn can auto-detect the link partners abilities and determine the highest speed/duplex conf iguration possible between the two devices. if the link partner does not support auto-n egotiation, then the rtl8201f/fl/fn will enable half-duplex mode and enter parallel detection mode. the rtl8201f/f l/fn will default to transmitting flp (fast link pulse) and wait for the link partner to respond. if the rtl8201f/fl/fn receives a flp, then the auto- negotiation process will continue. if it receives an nlp (normal link pulse), then the rtl8201f/fl/fn will change to 10mbps and half-duplex mode. if it receives a 100mbps idle pattern, it will change to 100mbps and half-duplex mode. 8.3.1. setting the medium type a nd interface mode to mac table 42. setting the medium type and interface mode to mac fxen rxdv operation mode h l fiber mode and mii mode h h fiber mode and rmii mode h x fiber mode and mii mode l l utp mode and mii mode l h utp mode and rmii mode l x utp mode and mii mode
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 32 track id: jatr-2265-11 rev. 1.4 8.4. led functions the rtl8201fn supports three led signals, a nd the rtl8201f and rtl8201fl support two led signals, in four configurable opera tion modes. the following sections describe the various led actions. 8.4.1. led and phy address as the phyad strap options share the led output pins , the external combinati ons required for strapping and led usage must be considered in order to a void contention. specifically, when the led outputs are used to drive leds directly, the active state of each output driver is dependent on the logic level sampled by the corresponding phyad input upon powe r-up/reset. for example, as fi gure 8 (left-side) shows, if a given phyad input is resistively pulled high then the corresponding out put will be configured as an active low driver. on the right side, we can see that if a given phyad i nput is resistivel y pulled low then the corresponding output will be configured as an ac tive high driver. the phy a ddress configuration pins should not be connected to gnd or vcc directly, but must be pulled high or low through a resistor (e.g., 4.7k ? ). if no led indications are needed, th e components of the led path (led+510 ? ) can be removed. phy address[:] = logical 1 phy address[:] = logical 0 led indication = active low led indication = active high figure 8. led and phy address configuration 8.4.2. link monitor the link monitor senses li nk integrity, such as link 10 , link 100 , link 10 /act, or link 100 /act. whenever link status is established, the specific link led pi n is driven low. once a cable is disconnected, the link led pin is driven high, indicati ng that no network connection exists.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 33 track id: jatr-2265-11 rev. 1.4 8.4.3. rx led in 10/100m mode, blinking of the rx led indi cates that receive ac tivity is occurring. figure 9. rx led 8.4.4. tx led in 10/100m mode, blinking of the tx led indi cates that transmit activity is occurring. figure 10. tx led
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 34 track id: jatr-2265-11 rev. 1.4 8.4.5. tx/rx led in 10/100m mode, blinking of the tx/rx led indicat es that both transmit an d receive activity is occurring. figure 11. tx/rx led 8.4.6. link/act led in 10/100m mode, blinking of the link/act led indicates that th e rtl8201f/fl/fn is linked and operating properly. when this led is high for extended periods, it indicates that a link problem exists. figure 12. link/act led
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 35 track id: jatr-2265-11 rev. 1.4 8.4.7. customized led the rtl8201f/fl/fn supports programmable leds in 10/100mbps mode. this function can be enabled/disabled via page7, re g19[3] register (figure 13). refer to section 7.17, page 23 for customized led register setting. figure 13. customized led with/without lpi led mode
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 36 track id: jatr-2265-11 rev. 1.4 8.4.8. eee led behavior eee idle mode: led continuous slow blinking. eee active mode: led fast and slow blinki ng (on packet transmission and reception). refer to table 29, page 23 for eee led enable setting. figure 14. eee led behavior 8.5. power down and link down power saving modes two types of power saving mode operation are suppor ted. this section describes how to implement each mode through software. table 43. power saving mode pin settings mode description pwd setting bit 11 of register 0 to 1 puts the rtl8201f /fl/fn into power down mode (pwd). this is the maximum power saving mode while the rtl8201f/fl/fn is still live. in pwd mode, the rtl8201f/fl/fn will turn off all analog/digita l functions except the mdc/mdio management interface. therefore, if the rtl8 201f/fl/fn is put into pwd mode and the mac wants to recall the phy, it must create the mdc/mdio timing by itself (this is done by software). ldps setting bit 15 of register 24 to 1 will put the r tl8201f/fl/fn into ldps (link down power saving) mode. in ldps mode, the rtl8201f/fl/fn will detect the link status to decide whether or not to turn off the transmit function. if the link is off, flp or 100mbps idle/10mbps nlp will not be transmitted. however, some signals similar to nlp will be transmitted. once the r eceiver detects leveled signals, it will stop the signal and transmit flp or 100mbps id le/10mbps nlp again. this can cut power used by 60%~80% when the link is down.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 37 track id: jatr-2265-11 rev. 1.4 8.6. 10m/100m transmit and receive 8.6.1. 100base-tx transmit and receive operation 100base-tx transmit transmit data in 4-bit nibbles (txd[3:0]) clocked at 25mhz (txc) is transformed into 5b symbol code (4b/5b encoding). scrambling, seri alizing, and conversion to 125mhz, and nrz to nrzi then takes place. after this process, the nrzi signal is passed to the mlt-3 encoder, then to the transmit line driver. the transmitter will first assert txen. before transm itting the data pattern, it will send a /j/k/ symbol (start-of-frame delimiter), the data symbol, and finally a /t/r/ symbol known as the end-of-frame delimiter. for better emi performance, the seed of the scrambler is based on the phy address. in a hub/switch environment, each rtl8201f/fl/fn will have different scrambler seeds and so spread the output of the mlt-3 signals. 100base-tx receive the received signal is compensated by the adaptive eq ualizer to make up for signal loss due to cable attenuation and inter symbol interference (isi). ba seline wander correction mo nitors the process and dynamically applies corrections to the process of signal equalization. the phase locked loop (pll) then recovers the timing information from the signals and from the receive clock. with this, the received signal is sampled to form nrzi (non-return-to-zero invert ed) data. the next steps are the nrzi to nrz (non- return-to-zero) process, unscrambling of the data, seri al to parallel and 5b to 4b conversion, and passing of the 4b nibble to the mii interface. 8.6.2. 100base-fx fiber transmit and receive operation the rtl8201f/fl/fn can be configured to 100b ase-fx mode via hardware configuration. the hardware 100base-fx setting take s priority over nway settings. a scrambler is not required in 100base-fx. 100base-fx transmit di-bits of txd are processed as 100base-tx except wi thout a scrambler before the nrzi stage. instead of converting to mlt-3 signals, as in 100base-tx, the serial data stream is driven out as nrzi pecl signals, which enter the fiber transc eiver in differential-pair form. 100base-fx receive the signal is received through pecl receiver inputs from the fiber transceiver and directly passed to the clock recovery circuit for data/clock recovery. th e scrambler/de-scrambler is bypassed in 100base-fx. 8.6.3. 10base-t transmit and receive operation 10base-t transmit transmit data in 4-bit nibbles (txd[ 3:0]) clocked at 2.5mhz (txc) is fi rst fed to a parallel-to-serial converter, then the 10mbps nrz si gnal is sent to a manchester en coder. the manchester encoder converts the 10mbps nrz data into a manchester enc oded data stream for the tp transmitter and adds a start of idle pulse (soi) at the end of the packet as specified in ieee 802.3. fi nally, the encoded data stream is shaped by a band-limited filter embedded in the rtl8201f/fl/fn and then transmitted.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 38 track id: jatr-2265-11 rev. 1.4 10base-t receive in 10base-t receive mode, the manchester decode r in the rtl8201f/fl/fn converts the manchester encoded data stream into nrz data by decoding the da ta and stripping off the so i pulse. the serial nrz data stream is then converted to a parallel 4-bit nibble signal (rxd[0:3]). 8.7. reset and transmit bias there are two rtl8201f/fl/fn reset types: 1. hardware reset: pull the phyrstb pin high fo r at least 150ms to access the rtl8201f/fl/fn registers. pull the phyrstb pin low for at least 10m s and then pull high. all re gisters will return to default values after a hardware reset. the medi a interface will disconnect and restart the auto- negotiation/parallel detection process. 2. software reset: set register 0 bit 15 to 1 for at least 20ms to access the r tl8201f/fl/fn registers. a software reset will only partially re set the registers, and will reset th e chip status to initializing. the rset pin must be pulled low by a 2.49k ? resistor with 1% accuracy to establish an accurate transmit bias. this will affect the signal quality of the transmit wavefo rm. keep its circuitry away from other clock traces and transmit/receive paths to avoid signal interference. 8.8. 3.3v power supply and voltage conversion circuit the rtl8201f/fl/fn is fabricated in a 0.11m proce ss. the core circuit needs to be powered by 1.1v, however, the digital io and dac ci rcuits need a 3.3v power supply. regulators are embedded in the rtl8201f/fl/fn to convert 3.3v to 1.1v. note: the internal linear regulator output voltage is 1.1v. a 1.05v is supplied when using external core power. the external 1.05v power suppl y is not suggested for the rtl8201f/fl as the internal regulators cannot be disabled (the rtl8201f/fl does not have an en_ldo_out pin to disa ble the internal 1.1v power supply), and the internal and ext ernal power sources may conflict. as with many commercial voltage conversion devices, th e 1.1v output pin of this circuit requires the use of an output capacitor (0.1f x5r low-esr ceramic capacitor) as part of the device frequency compensation. the analog and digital ground planes should be as large and intact as possible. if the ground plane is large enough, the analog and digital grounds can be separated, which is the ideal configuration. however, if the total ground plane is not sufficiently large, partition of the ground plan e is not a good idea. in this case, all the ground pins can be connected together to a larger single and intact ground plane. note: the embedded 1.1v ldo is designed for phyceiver device internal use only. do not provide this power to other devices.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 39 track id: jatr-2265-11 rev. 1.4 8.9. automatic polarity correction the rtl8201f/fl/fn automatically corrects polarity errors on the receive pairs in 10base-t mode (polarity is irrelevant in 100base-tx mode). in 10base-t mode, pol arity errors are co rrected based on the detection of validly spaced link pulses. detection begins during the mdi crossover detection phase and locks when the 10base-t link is up. the polar ity becomes unlocked when the link goes down. 8.10. far end fault indication the mii reg.1.4 (remote fault) is the far end fault indication (fefi) bit when 100fx m ode is enabled, and indicates when a fefi has been detected. fefi is an alternative in-band signaling method that is composed of 84 consecutive 1s followed by one 0 . when the rtl8201f/fl/fn detects this pattern three times, reg.1.4 is set, which means the transmit pa th (the remote sides receive path) has a problem. on the other hand, if an incoming signal fails to cause a link ok, the rtl8201f/fl/fn will start sending this pattern, which in turn causes the remote si de to detect a far end fault. this means that the receive path has a problem from the point of view of the rtl8201f /fl/fn. the fefi mechanism is used only in 100base-fx mode. 8.11. wake-on-lan (wol) 8.11.1. magic packet and wake-up frame format the rtl8201f/fl/fn can monitor the network for a wake-up frame or a magic packet, and notify the system via the pmeb (power management event; b m eans low active) pin when such a packet or event occurs. the system can then be restored to a normal state to process incoming jobs. the pmeb pin must be connected with a 4.7k-ohm resistor and pulle d up to 3.3v. when the wake-up frame or a magic packet is sent to the phy, the pmeb pin will be se t low to notify the system to wake up. refer to the wol application note for details. magic packet wake-up occurs only wh en the following conditions are met: ? the destination address of the received magic packet is accepta ble to the rtl8201f/fl/fn, e.g., a broadcast, multicast, or unicast packet addressed to the current rtl8201f/fl/fn. ? the received magic packet does not contain a crc error. ? the magic packet pattern matches; i.e., 6 * ffh + misc (can be none) + 16 * did (destination id) in any part of a valid ethernet packet. a wake-up frame event occurs only when the following conditions are met: ? the destination address of the received wake-up frame is accepta ble to the rtl8201f/fl/fn, e.g., a broadcast, multicast, or unicast a ddress to the current rtl8201f/fl/fn. ? the received wake-up frame does not contain a crc error.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 40 track id: jatr-2265-11 rev. 1.4 ? the 16-bit crc of the received wake-up frame matches the 16-bit crc of the sample wake-up frame pattern given by the local machines os. or , the rtl8201f/fl/fn is configured to allow direct packet wake up, e.g., a broadcast, multicast, or unicast network packet. note 1: 16-bit crc: the rtl8201f/fl/fn supports eight long-wake-up frames (covering 128 mask bytes from offset 0 to 127 of any in coming network packet). crc16 polynomial=x 16 +x 12 +x 5 +1. note 2: refer to the wol applicat ion note for detailed wake-on-lan register settings and waveform timings. 8.11.2. active low wake-on-lan when the phy receives a wake-up frame or a magic packet from the link partner, the pmeb pin will go low and the mac will wake up after a t cycle. the pm eb pin will be reset to high via the system or mac (figure 15 and figure 16). refer to the wol application note for details. figure 15. active low when receiving a magic packet figure 16. active low when receiving a wake-up frame
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 41 track id: jatr-2265-11 rev. 1.4 8.11.3. pulse low wake-on-lan when the phy receives a wake-up frame or a magic packet from the link partner, the pmeb pin will go low for a period (84ms, 168ms (default), 336ms, or 672ms; set through the mdc/mdio), and will wake up after a t cycle (figure 17 and figure 18). refer to the wol application note for details. magic packet period controlled by the phy wol enable from link partner pmeb t figure 17. pulse low when receiving a magic packet wake up frame period controlled by the phy wol enable from link partner pmeb t figure 18. pulse low when receiving a wake-up frame
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 42 track id: jatr-2265-11 rev. 1.4 8.11.4. wake-on-lan pin types (mii mode) table 44. wake-on-lan pin types (mii mode) name type normal wol enable 100m 10m idle txc o/pd 25m clk output 2.5m clk output 2.5m clk output o (2.5m/25m)/l/pd 1 txen i/pd i i i i/pd txd[0:3] i/pd i i i i/pd rxc o/pd 25m clk output 2.5m clk output 2.5m clk output o (2.5m/25m)/pd 2 col li/o/pd o o o o or pd 2 crs li/o/pd o o o o or pd 2 rxdv li/o/pd o o o o or pd 2 rxd[0:2] o/pd o o o o or pd 2 rxd[3] li/o/pd o o o o or pd 2 rxer li/o/pd o o o o or pd 2 mdc i/pu i i i i/pu mdio io/pu io io io io/pu note 1: if tx isolate=1, the txc is halted and the pin type is l. set page0, register0, and bit10=1 to change the txc pin type to pd. note 2: if rx isolate=1, all the mii rx interfaces are halted and the pin types are pd. 8.11.5. wake-on-lan pin types (rmii mode) table 45. wake-on-lan pin types (rmii mode) name type normal wol enable 100m 10m idle txc (ref_clk) 1 io/pd 50m clk input/output 50m clk input/output 50m clk input/output i/o (50m) 2 txen i/pd i i i i/pd txd[0:1] i/pd i i i i/pd crs_dv li/o/pd o o o o or pd 3 rxd[0:1] o/pd o o o o or pd 3 rxer li/o/pd o o o o or pd 3 mdc i/pu i i i i/pu mdio io/pu io io io io/pu note 1: if txc (ref_clk) is in input mode (mac to phy), the ref _clk cannot halt at wol enable. note 2: when ref_clk is in output mode (phy to mac), th e ref_clk cannot halt (always toggles 50mhz out). to set the txc pin type to pd, set page0, register0, bit10=1. note 3: if rx isolate=1, all rmii rx interfaces are halted and the pin types are pd.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 43 track id: jatr-2265-11 rev. 1.4 8.12. energy efficient ethernet (eee) the rtl8201f/fl/fn supports ieee 802.3az-2010, also k nown as energy efficien t ethernet (eee), at 10mbps and 100mbps. it provides a protocol to coordinate transitions to/from a lower power consumption level (low power idle mode) based on link utilization. when no packets are being transmitted, the system goes to low power idle m ode to save power. when packets need to be transmitted, the system returns to normal mode, a nd does this without changing the link status and without dropping/corrupting frames. to save power, when the system is in low power id le mode, most of the circ uits are disa bled; however, the transition time to/from low power idle mode is kept small enough to be transparent to upper layer protocols and applications. eee also specifies a negotiation method to enable li nk partners to determine whether eee is supported. refer to http://www.ieee802.org/3/az /index.html for more details. refer to the rtl8201(f_fl_fn)_ethernet_tran sceiver_(r)mii_eee_app_note for eee mii/rmii power saving mode register settings. 8.13. spread spectrum clock (ssc) the rmii ref_clk path can be a source of emi noise. spread spectrum clock (ssc) spreads the ref_clk signal across a wide r bandwidth, reducing the peak radiat ed energy at any one frequency, and lowering unwanted emi noise. the ssc function is enabled by default when usi ng rmii ref_clk output mode (see section 7.21 page 7 register 24 spread spectru m clock register, page 25). figure 19. spectrum spread clock
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 44 track id: jatr-2265-11 rev. 1.4 9. characteristics 9.1. dc characteristics 9.1.1. absolute maximum ratings table 46. absolute maximum ratings symbol description minimum maximum unit dvdd33, avdd33 supply voltage 3.3v -0.4 +3.7 v dvdd10, dvdd10out, avdd10out supply voltage 1.05v* -0.1 +1.26 v dc input input voltage -0.3 corresponding supply voltage +0.5v v dc output output voltage -0.3 corresponding supply voltage +0.5v v n/a storage temperature -55 +125 c note: the internal linear regulator output voltage is 1.1v. 9.1.2. recommended operating conditions table 47. recommended operating conditions description pins minimum typical maximum unit dvdd33, avdd33 2.97 3.30 3.63 v supply voltage vdd dvdd10, dvdd10out, avdd10out 1.00 1.05* 1.16 v ambient operating temperature t a - 0 - 70 c maximum junction temperature - - - 125 c note: the internal linear regulator output voltage is 1.1v.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 45 track id: jatr-2265-11 rev. 1.4 9.1.3. power on and phy reset sequence the rtl8201f/fl/fn needs 150ms power on time. af ter 150ms it can access the phy register from mdc/mdio. figure 20. power on and phy reset sequence table 48. power on and phy reset sequence symbol description minimum maximum rt1 3.3v rise time@ power on sequence 100s - rt2 1.05v rise time@ power on and phy reset sequence 100s - rt3 phyrstb de-assert after phy_3.3v stable 80s - note: rt2 requires 100s rise time only when using an external 1.05v power supply.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 46 track id: jatr-2265-11 rev. 1.4 9.1.4. rmii input mode power dissipation the whole system power dissipation (including regulator loss) is shown in table 49. table 49. rmii input mode power dissipation (whole system) symbol condition rtl8201f rtl8201fn rtl8201fl unit p 10idle 10base-t idle (eee not enabled) 36.3 36.3 36.3 mw p 10f 10base-t full duplex 108.9 118.8 108.9 mw p 100idle 100base-t idle (eee not enabled) 148.5 151.8 155.1 mw p 100idleeee 100base-t idle with eee 56.1 56.1 62.7 mw p 100f 100base-t full duplex 174.9 178.2 178.2 mw p ldps link down power saving 20.328 17.985 23.1 mw p phyrst phy reset 3.3 3.3 3.3 mw note: setting page 4 register 21 bit12 to 1 will reduce power consumption when the system is idle. 9.1.5. input voltage: vcc table 50. input voltage: vcc symbol condition minimum maximum ttl v ih input high voltage - 0.5*vcc vcc+0.5v ttl v il input low voltage - -0.5v 0.7v ttl v oh output high voltage ioh=-8ma 0.65*vcc vcc ttl v ol output low voltage iol=8ma - 0.7v ttl i oz tri-state leakage vout=vcc or gnd -110a 10a i in input current vin=vcc or gnd -1a 10a i pl input current with internal weakly pulled low resistor vin=vcc or gnd -1a 100a i ph input current with internal weakly pulled high resistor vin=vcc or gnd -110a 10a pecl v ih pecl input high voltage - vdd-1.16v vdd-0.88v pecl v il pecl input low voltage - vdd-1.81v vdd-1.47v pecl v oh pecl output high voltage - vdd-1.02v - pecl v ol pecl output low voltage - - vdd-1.62v
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 47 track id: jatr-2265-11 rev. 1.4 9.2. ac characteristics all output timing assumes equivalent loading between 10pf and 25pf that includes pcb layout traces and other connected devices (e.g., mac). 9.2.1. mii transmission cycle timing figure 21. mii interface setup/hold time definitions figure 22 and figure 23 and show an example of a packet transfer from mac to phy on the mii interface. txclk v ih(min) v il(max) txd[0:3] txen v ih(min) v il(max) t 4 t 5 t 3 t 1 t 2 figure 22. mii transmission cycle timing-1 txclk txen txd[0:3] crs t 6 t 7 figure 23. mii transmission cycle timing-2
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 48 track id: jatr-2265-11 rev. 1.4 table 51. mii transmission cycle timing symbol description minimum typical maximum unit 100mbps 14 20 26 ns t 1 txclk high pulse width 10mbps 140 200 260 ns 100mbps 14 20 26 ns t 2 txclk low pulse width 10mbps 140 200 260 ns 100mbps - 40 - ns t 3 txclk period 10mbps - 400 - ns 100mbps 10 - - ns t 4 txen, txd[0:3] setup to txclk rising edge 10mbps 5 - - ns 100mbps 0 - - ns t 5 txen, txd[0:3] hold after txclk rising edge 10mbps 0 - - ns 100mbps - - 40 ns t 6 txen sampled to crs high 10mbps - - 400 ns 100mbps - - 160 ns t 7 txen sampled to crs low 10mbps - - 2000 ns 9.2.2. mii reception cycle timing figure 24 and figure 25 show an example of a packet transfer from phy to mac on the mii interface. rxclk rxd[0:3] rxdvrxer v ih(min) v il(max) v ih(min) v il(max) t 4 t 5 t 1 t 3 t 2 figure 24. mii reception cycle timing-1 rxclk rxdv rxd[0:3] crs tprx+- t 8 t 6 t 7 t 9 figure 25. mii reception cycle timing-2
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 49 track id: jatr-2265-11 rev. 1.4 table 52. mii reception cycle timing symbol description minimum typical maximum unit 100mbps 14 20 26 ns t 1 rxclk high pulse width 10mbps 140 200 260 ns 100mbps 14 20 26 ns t 2 rxclk low pulse width 10mbps 140 200 260 ns 100mbps - 40 - ns t 3 rxclk period 10mbps - 400 - ns 100mbps 10 - - ns t 4 rxer, rxdv, rxd[0:3] setup to rxclk rising edge 10mbps 10 - - ns 100mbps 10 - - ns t 5 rxer, rxdv, rxd[0:3] hold after rxclk rising edge 10mbps 10 - - ns 100mbps - - 130 ns t 6 receive frame to crs high 10mbps - - 2000 ns 100mbps - - 240 ns t 7 end of receive frame to crs low 10mbps - - 1000 ns 100mbps - - 150 ns t 8 receive frame to sampled edge of rxdv 10mbps - - 3200 ns 100mbps - - 120 ns t 9 end of receive frame to sampled edge of rxdv 10mbps - - 1000 ns 9.2.3. rmii transmission and re ception cycle timing mac rtl8201f-vb/ rtl8201fl-vb/ rtl8201fn-vb mac to phy setup/hold time phy to mac output delay time rmii tx refclk rmii rx figure 26. rmii interface setup, hold time, and output delay time definitions
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 50 track id: jatr-2265-11 rev. 1.4 figure 27. rmii transmission and reception cycle timing table 53. rmii transmission and reception cycle timing symbol description minimum typical maximum unit refclk frequency frequency of reference clock - 50 - mhz refclk duty cycle duty cycl e of reference clock 35 - 65 % t_ipsu_tx_rmii txd[1:0]/txen setup time to refclk 4 - - ns t_iphd_tx_rmii txd[1:0]/txen hold time from refclk 2 - - ns t_ophd_rx_rmii rxd[1:0]/crs_dv/rxer output delay time from refclk 2 - - ns note 1: rmii tx timing can be adjusted by setting page7, register16[11:8]; the minimum adjustable resolution is 2ns. any changes for these bits are not recommended as the default value is the optimum setting. note 2: rmii rx timing can be adjusted by setting page7, register16[7:4]; the minimum adj ustable resolution is 2ns. any changes for these bits are not recommended as the default value is the optimum setting.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 51 track id: jatr-2265-11 rev. 1.4 9.2.4. mdc/mdio timing figure 28. mdc/mdio interface setup, hold time, and valid from mdc rising edge time definitions figure 29. mdc/mdio timing table 54. mdc/mdio timing symbol description minimum maximum unit t 1 mdc high pulse width 160 - ns t 2 mdc low pulse width 160 - ns t 3 mdc period 400 - ns t 4 mdio setup to mdc rising edge 10 - ns t 5 mdio hold time from mdc rising edge 10 - ns t 6 mdio valid from mdc rising edge 0 300 ns
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 52 track id: jatr-2265-11 rev. 1.4 9.2.5. transmission without collision figure 30 shows an example of a pack et transfer from mac to phy. figure 30. mac to phy tran smission without collision 9.2.6. reception without error figure 31 shows an example of a pack et transfer from phy to mac. figure 31. phy to mac reception without error
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 53 track id: jatr-2265-11 rev. 1.4 9.3. crystal characteristics table 55. crystal characteristics symbol description/condition minimum typical maximum unit f ref parallel resonant crystal reference frequency, fundamental mode, at-cut type. - 25 - mhz f ref stability parallel resonant crystal frequency stability, fundamental mode, at-cut type. t a =0 c~70 c. -30 - +30 ppm f ref tolerance parallel resonant crystal frequency tolerance, fundamental mode, at-cut type. t a =25 c. -50 - +50 ppm f ref duty cycle reference clock input duty cycle. 40 - 60 % esr equivalent series resistance. - - 30 ? dl drive level. - - 0.3 mw jitter broadband peak-to-peak jitter 1, 2 - - 500 ps note 1: 25khz to 25mhz rms < 3ps. note 2: broadband rms < 9ps. 9.4. oscillator requirements table 56. oscillator requirements parameter condition minimum typical maximum unit frequency - - 25/50 - mhz frequency stability ta = 0c~+70c -30 - 30 ppm frequency tolerance ta = 25c -50 - 50 ppm duty cycle - 40 - 60 % broadband peak-to-peak jitter 1, 2 - - - 500 ps vpeak-to-peak - 3.15 3.3 3.45 v rise time (10%~90%) - - - 10 ns fall time (10%~90%) - - - 10 ns operating temperature range - 0 - 70 c note 1: 25khz to 25mhz rms < 3ps. note 2: broadband rms < 9ps.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 54 track id: jatr-2265-11 rev. 1.4 9.5. clock requirements table 57. clock requirements parameter minimum typical maximum unit frequency - 25/50 - mhz frequency stability -30 - 30 ppm frequency tolerance -50 - 50 ppm duty cycle 40 - 60 % broadband peak-to-peak jitter 1, 2 - - 500 ps vpeak-to-peak 3.15 3.3 3.45 v rise time (10%~90%) - - 10 ns fall time (10%~90%) - - 10 ns note 1: 25khz to 25mhz rms < 3ps. note 2: broadband rms < 9ps. 9.6. transformer characteristics table 58. transformer characteristics parameter transmit end receive end turn ratio 1:1 ct 1:1 ct inductance (min.) 350h @ 8ma 350h @ 8ma
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 55 track id: jatr-2265-11 rev. 1.4 10. mechanical dimensions 10.1. rtl8201f (qfn-32) symbol dimension in mm dimension in inch min nom max min nom max a 0.75 0.85 1.00 0.030 0.034 0.039 a 1 0.00 0.02 0.05 0.000 0.001 0.002 a 3 0.20ref 0.008ref b 0.18 0.25 0.30 0.007 0.010 0.012 c - - 0.6 - - 0.024 d/e 5.00bsc 0.197bsc d 2 /e 2 3.10 3.35 3.60 0.122 0.132 0.142 e 0.50bsc 0.020bsc l 0.30 0.40 0.50 0.012 0.016 0.020 note 1: controlling dime nsion: millimeter (mm). note 2: reference document: jedec mo-220.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 56 track id: jatr-2265-11 rev. 1.4 10.2. rtl8201fl (lqfp-48) symbol dimension in mm dimension in inch min nom max min nom max a - - 1.60 - - 0.063 a 1 0.05 - 0.15 0.002 - 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 d/e 9.00bsc 0.354bsc d 1 /e 1 7.00bsc 0.276bsc e 0.50bsc 0.020bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00ref 0.039ref note 1: controlling dime nsion: millimeter (mm). note 2: reference document: jedec ms-026.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 57 track id: jatr-2265-11 rev. 1.4 10.3. rtl8201fn (qfn-48) symbol dimension in mm dimension in inch min nom max min nom max a 0.75 0.85 1.00 0.030 0.034 0.039 a 1 0.00 0.02 0.05 0.000 0.001 0.002 a 3 0.20ref 0.008ref b 0.15 0.20 0.25 0.006 0.008 0.010 d/e 6.00bsc 0.236bsc d 2 /e 2 4.05 4.4 4.65 0.163 0.173 0.183 e 0.40bsc 0.016bsc l 0.30 0.40 0.50 0.012 0.016 0.020 notes 1: controlling dimension: millimeter (mm). note 2: reference document: jedec mo-220.
rtl8201f/rtl8201fl/rtl8201fn datasheet single-chip/port 10/100m ethernet phyceiver with auto mdix 58 track id: jatr-2265-11 rev. 1.4 11. ordering information table 59. ordering information part number package status RTL8201F-VB-CG 32-pin qfn green package (for details see table 60 below) rtl8201fl-vb-cg 48-pin lqfp green package (for details see table 60 below) rtl8201fn-vb-cg 48-pin qfn green package (for details see table 60 below) note: see page 5, 6, and 7 for package identification. 11.1. rtl8201f series selection guide table 60. rtl8201f series selection guide part number interface package wol (pmeb pin) ref_clk direction h/w strap eee intb number of leds co-layout solution RTL8201F-VB-CG rmii mii q fn 32 yes yes yes yes* 2 rtl82 01 e- vc rtl8201fl-vb-cg rmii mii lq f p48 yes yes yes yes 2 rtl8201el rtl8201el-vc rtl8201fn-vb-cg rmii mii q fn 48 yes yes yes yes 3 rtl8211d-vb rtl8211e-vb rtl8201en-vc note: the rtl8201f intb pin is used for the interrupt function only when in the rmii mode. realtek semiconductor corp. headquarters no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan. tel: 886-3-578-0211 fax: 886-3-577-6047 www.realtek.com


▲Up To Search▲   

 
Price & Availability of RTL8201F-VB-CG

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X